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HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11582 READING AND ANALYSING THE SYSTEM REQUIREMENTS AND ARCHITECTURE REQUIREMENT DOCUMENTS.DEVELOPING DETAILED TEST AND COVERAGE PLANS BASED ON THE ARCHITECTURE AND MICRO-ARCHITECTURE.DEVELOPING VERIFICATION METHODOLOGY.DEVELOPING VERIFICATION ENVIRONMENT DEVELOPMENT AND MAINTENANCE IN SYSTEMVERILOG/UVM/SYSTEMC/C++, INCLUDING ALL THE RESPECTIVE COMPONENTS.EXECUTING VERIFICATION PLANS, INCLUDING DESIGN BRING-UP, DV ENVIRONMENT BRING-UP, REGRESSIONS AND DEBUG OF THE TEST FAILURES.USING THE STANDARD TOOLS AND FLOWS OF THE VERIFICATION PROCESS CREATE AND EXECUTE TESTCASES TO VERIFY THE FUNCTIONALITY, PERFORMANCE, AND ROBUSTNESS IN EMBEDDED C AND SV.IDENTIFY, ISOLATE, AND DEBUG ISSUES FOUND DURING VERIFICATION, LEVER...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11574 READING AND ANALYSING THE SYSTEM REQUIREMENTS AND ARCHITECTURE REQUIREMENT DOCUMENTS.DEVELOPING VERIFICATION ENVIRONMENT DEVELOPMENT AND MAINTENANCE IN SYSTEMVERILOG/UVM/SYSTEMC/C++, INCLUDING ALL THE RESPECTIVE COMPONENTS.EXECUTING VERIFICATION PLANS, INCLUDING DESIGN BRING-UP, DV ENVIRONMENT BRING-UP, REGRESSIONS AND DEBUG OF THE TEST FAILURES.USING THE STANDARD TOOLS AND FLOWS OF THE VERIFICATION PROCESS.CREATE AND EXECUTE TESTCASES TO VERIFY THE FUNCTIONALITY, PERFORMANCE, AND ROBUSTNESS IN EMBEDDED C AND SV.IDENTIFY, ISOLATE, AND DEBUG ISSUES FOUND DURING VERIFICATION.WORK CLOSELY WITH CROSS-FUNCTIONAL TEAMS TO ACHIEVE VERIFICATION CLOSURE, CONDUCTING COVERAGE ANALYSIS, BUG TRACKING, AND REGRESSION TE...

AS A FUNCTIONAL VERIFICATION ENGINEER, YOU WILL BE INTERFACING WITH ARCHITECTURE, DESIGN, PHYSICAL IMPLEMENTATION AND SOFTWARE TEAMS IN ORDER TO MAKE SURE THAT THE SYSTEMS ARE PERFORMING TO THE HIGHEST LEVEL. YOUR WORK MAY INVOLVE HIGH-LEVEL MODELLING, UVM, HW/SW CO-DEBUG, SIMULATION ACCELERATION SUPPORT. THE ROLE:READING AND ANALYSING THE SYSTEM REQUIREMENTS AND ARCHITECTURE REQUIREMENT DOCUMENTS. DEVELOPING VERIFICATION ENVIRONMENT DEVELOPMENT AND MAINTENANCE IN SYSTEMVERILOG/UVM/SYSTEMC/C++, INCLUDING ALL THE RESPECTIVE COMPONENTS SUCH AS STIMULUS, CHECKERS, ASSERTIONS, TRACKERS, AND COVERAGE.EXECUTING VERIFICATION PLANS, INCLUDING DESIGN BRING-UP, DV ENVIRONMENT BRING-UP, REGRESSIONS AND DEBUG OF THE TEST FAILURES. USING THE STANDARD TOOLS AND FLOWS OF THE VERIFICATION PROCESS (SIMULAT...

KEY RESPONSIBILITIES: READING AND ANALYSING THE SYSTEM REQUIREMENTS AND ARCHITECTURE REQUIREMENT DOCUMENTS.DEVELOPING DETAILED TEST AND COVERAGE PLANS BASED ON THE ARCHITECTURE AND MICRO-ARCHITEC-TURE.DEVELOPING VERIFICATION METHODOLOGY, ENSURING SCALABILITY AND PORTABILITY ACROSS ENVIRON-MENTS.DEVELOPING VERIFICATION ENVIRONMENT DEVELOPMENT AND MAINTENANCE IN SYSTEMVERI-LOG/UVM/SYSTEMC/C++, INCLUDING ALL THE RESPECTIVE COMPONENTS SUCH AS STIMULUS, CHECKERS, ASSERTIONS, TRACKERS, AND COVERAGE.EXECUTING VERIFICATION PLANS, INCLUDING DESIGN BRING-UP, DV ENVIRONMENT BRING-UP, REGRES-SIONS AND DEBUG OF THE TEST FAILURES.USING THE STANDARD TOOLS AND FLOWS OF THE VERIFICATION PROCESS.CREATE AND EXECUTE TESTCASES TO VERIFY THE FUNCTIONALITY, PERFORMANCE, AND ROBUSTNESS IN EM-BEDDED C AND SV.IDENT...