49 Jobs found

COMPILER ENGINEER JOB RESPONSIBILITIES: MAKE INDEPENDENT TECHNICAL CONTRIBUTIONS TO HELP THEIR TEAM DELIVER ITS COMMITMENTS. IN PARTICULAR: ¿WRITE CODE TO EXTEND COMPILER FRAMEWORKS (E.G., GCC, LLVM), ENABLING USAGE OF NOVEL HARDWARE FEATURES AND ACCELERATION, AND IMPROVING THE QUALITY OF CODE GENERATED FOR THESE TARGETS.¿THIS INCLUDES BOTH ¿TRADITIONAL(HIGH-LEVEL LANGUAGE TO BINARY) COMPILERS AS WELL AS THOSE MANIPULATING ML INTERMEDIATE REPRESENTATIONS (E.G., MODEL GRAPHS) INTERACT WITH ICS FROM THEIR AND OTHER PROJECTS TO UNBLOCK THEMSELF, OR TO REACH CONSENSUS ON SMALL TECHNICAL TOPICS. IN PARTICULAR: ¿WORK WITH ML/AI AND HARDWARE TEAMS, CONNECTING THEIR RESPECTIVE REQUIREMENTS AND OFFERINGS, INFLUENCING HARDWARE/SOFTWARE CO-DESIGN. ¿IN OTHER CASES, UNDERSTAND ML/AI WORKLOADS, BOTH IND...

KEY RESPONSIBILITIES:· RESEARCH, DESIGN, AND IMPLEMENT MULTI-AGENT LLM-BASED ARCHITECTURES TO SOLVE REAL-WORLD AI CHALLENGES.· DEVELOP AND OPTIMIZE ALGORITHMS FOR AGENT COORDINATION, COMMUNICATION, AND COLLABORATION IN COMPLEX ENVIRONMENTS.· WORK WITH CUTTING-EDGE AI TECHNIQUES SUCH AS REINFORCEMENT LEARNING, SELF-SUPERVISED LEARNING, AND META-LEARNING TO ENHANCE MULTI-AGENT PERFORMANCE.· COLLABORATE WITH HARDWARE AND SOFTWARE ENGINEERS TO CO-DESIGN AI MODELS OPTIMIZED FOR OPENCHIP¿S CUSTOM SILICON SOLUTIONS.· EXPERIMENT WITH DECENTRALIZED AI MODELS AND FEDERATED LEARNING APPROACHES FOR MULTI-AGENT SYSTEMS.· IMPLEMENT LARGE-SCALE DISTRIBUTED TRAINING PIPELINES FOR MULTI-AGENT REINFORCEMENT LEARNING.· CONDUCT PERFORMANCE ANALYSIS AND BENCHMARKING OF AI WORKLOADS ON CUSTOM ACCELERATORS.· STA...

KEY RESPONSIBILITIES:LEAD AND MENTOR A TEAM OF AI ENGINEERS, FOSTERING INNOVATION AND TECHNICAL EXCELLENCE.DEFINE AND OVERSEE THE ROADMAP FOR AI DEVELOPMENT, ENSURING ALIGNMENT WITH OPENCHIP¿S LONG-TERM VISION.ARCHITECT AND IMPLEMENT SCALABLE BACKEND SYSTEMS THAT SUPPORT AI-DRIVEN FUNCTIONALITIES, LEVERAGING MODERN FRAMEWORKS AND METHODOLOGIES.OPTIMIZE AI WORKLOADS FOR CUSTOM SILICON, WORKING CLOSELY WITH HARDWARE AND SOFTWARE TEAMS.RESEARCH AND INTEGRATE ADVANCED AI TECHNIQUES SUCH AS REINFORCEMENT LEARNING, SELF-SUPERVISED LEARNING, AND FEDERATED LEARNING.DESIGN AND MANAGE DISTRIBUTED AI SYSTEMS, ENSURING EFFICIENT TRAINING AND INFERENCE FOR LARGE-SCALE MODELS.COLLABORATE WITH CROSS-FUNCTIONAL TEAMS TO CO-DEVELOP AI SOLUTIONS THAT ENHANCE CHIP PERFORMANCE AND EFFICIENCY.STAY AHEAD OF AI ...

KEY RESPONSIBILITIES:DEVELOP, OPTIMIZE, AND MAINTAIN SCALABLE BACKEND SERVICES SUPPORTING AI-DRIVEN APPLICATIONS AND PIPELINES.DESIGN AND IMPLEMENT APIS FOR AI MODEL INFERENCE, TRAINING, AND DATA PROCESSING.COLLABORATE WITH AI AND HARDWARE ENGINEERS TO INTEGRATE AI FUNCTIONALITIES INTO CUSTOM SILICON SOLUTIONS.WORK WITH DATABASES AND STORAGE SOLUTIONS TO MANAGE AND PROCESS LARGE-SCALE AI DATASETS EFFICIENTLY.ENSURE SECURITY, PERFORMANCE, AND RELIABILITY IN AI-BASED BACKEND ARCHITECTURES.DEPLOY AND MANAGE AI MODELS IN CLOUD AND ON-PREMISE ENVIRONMENTS, OPTIMIZING FOR PERFORMANCE AND COST.STAY UP TO DATE WITH ADVANCEMENTS IN AI SOFTWARE ENGINEERING AND BACKEND TECHNOLOGIES TO BRING INNOVATIVE SOLUTIONS INTO OPENCHIP¿S AI STRATEGY. QUALIFICATIONS:BSC OR MSC IN COMPUTER SCIENCE, SOFTWARE ENGIN...

KEY RESPONSIBILITIES:· RESEARCH, DEVELOP, AND IMPLEMENT MODEL OPTIMIZATION TECHNIQUES SUCH AS QUANTIZATION, PRUNING, AND DISTILLATION TO IMPROVE AI MODEL EFFICIENCY.· DESIGN AND OPTIMIZE AI MODELS FOR DEPLOYMENT ON (CUSTOM) AI ACCELERATORS.· WORK CLOSELY WITH HARDWARE AND SOFTWARE TEAMS TO CO-DESIGN AI MODELS THAT LEVERAGE  UNIQUE SILICON CAPABILITIES.· DEVELOP STRATEGIES FOR REDUCING MEMORY FOOTPRINT, ENERGY CONSUMPTION, AND LATENCY IN AI INFERENCE.· BENCHMARK AND ANALYZE AI WORKLOADS ON VARIOUS ARCHITECTURES TO DRIVE OPTIMIZATION STRATEGIES.· STAY UP TO DATE WITH THE LATEST ADVANCEMENTS IN AI MODEL OPTIMIZATION, EDGE AI DEPLOYMENT, AND HARDWARE-AWARE NEURAL NETWORK DESIGN.· PARTICIPATE IN TECHNICAL DISCUSSIONS AND CONTRIBUTE TO OUR¿S AI RESEARCH AND DEVELOPMENT ROADMAP. QUALIFICATIONS:BS...

KEY RESPONSABILITIES:MANAGE A TEAM OF ENGINEERS WORKING IN THE RELEVANT TECHNICAL SPACE. IN PARTICULAR:CREATE A WELCOMING WORK ENVIRONMENT IN THEIR ORG AND STRIVE FOR REPORTSMOTIVATION, WELL-BEING, AND PROFESSIONAL GROWTH OPPORTUNITIES.PROVIDE TECHNICAL AND PROFESSIONAL GUIDANCE TO THEIR REPORTS. GIVE FEEDBACK, PRIORITIES, AND HIGHER- LEVEL CONTEXT.TAKE PART IN TASK TRACKING AND ASSIGNMENT, MONITORING THEIR REPORTSWORKLOADS AS WELL AS HOW TASKS ARE CONTRIBUTING TO DEVELOPMENT AND BUSINESS GOALS.HOST REGULAR 1:1 AND TEAM-WIDE MEETINGS FOR FREQUENT COMMUNICATION AND OVERALL TEAM AWARENESS.HOST REGULAR PERFORMANCE CONVERSATIONS WITH REPORTS AND COMPLETE THE PERIODICAL PERFORMANCE APPRAISAL PROCESS FOR THEIR TEAM. DETERMINE CLEAR PERFORMANCE GOALS, KEEP TRACK OF THEIR PROGRESS, AND TAKE PART I...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11570 THE SENIOR CAD ENGINEER MUST DEVELOP DEPLOY, AND MAINTAIN ENGINEERING SOFTWARE SOLUTIONS SUCH AS COMMON COMPUTER AIDED DESIGN (CAD).  CONFIGURE, TEST, AND DEPLOY CAD AND SIMULATION SOFTWARE APPLICATIONS.PROVIDE CUSTOMER SERVICE INCLUDING, BUT NOT LIMITED TO, TROUBLESHOOT ENGINEERING SOFTWARE APPLICATION ISSUES.DEVELOP AND MANAGE ENGINEERING PROCESS DOCUMENTATION.DEVELOP AND PROVIDE ENGINEERING SOFTWARE TRAINING AND CONSULTING SERVICES TO GLOBAL ENGINEERS.CREATE, MANAGE, UPDATE SCRIPTS TO FACILITATE THE IMPORT AND EXPORT OF DATA BETWEEN DIFFERENT CAD PROGRAMS OR BETWEEN CAD AND OTHER SOFTWARE TOOLS, ENABLING INTEROPERABILITY.SUPPORT, ENHANCE, AND MAINTAIN PDKS AND VARIOUS ANALOG/MIXED-SIGNAL DESIGN TOOLS.· ...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11619 WE ARE ACTIVELY SEEKING A DESIGN ENGINEER TO JOIN OUR DYNAMIC AND GROWING DIGITAL DESIGN TEAM. JOB RESPONSIBILITIES: RESPONSIBILITIES INCLUDE BUT NOT LIMITED TO: TO WRITE RTL CODE FOR SPECIFIC/GENERIC IP STARTING FROM IP SPECIFICATION/TO VALIDATE THE IP TO ENSURE THAT IT MEET THE SPECIFICATION REQUIREMENTS/TO WRITE THE FINAL DESIGN DOCUMENTATION ENSURING THE EASY INTEGRATION OF THE IP INSIDE A COMPLEX SOC./TO WORK IN TIGHT COLLABORATION WITH EMULATION, VERIFICATION, AND VALIDATION DEVELOPMENT TEAMS TO ENSURE BUG FREE DESIGN/TO WORK WITH POST-SILICON VALIDATION, MANUFACTURING, PLATFORM, AND SOFTWARE STAKEHOLDERS THROUGHOUT THE PRODUCT DEVELOPMENT. REQUIRED SKILLS, QUALIFICATIONS AND EXPERIENCE: MASTER'S DEG...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11555 ARCHITECT, DESIGN, AND OPTIMIZE THE FABRIC INTERCONNECTS AND SYSTEM-LEVEL COMPONENTS FOR RISC-V-BASED ACCELERATORS.COLLABORATE CLOSELY WITH HARDWARE AND SOFTWARE TEAMS TO ENSURE SEAMLESS INTEGRATION OF ACCELERATOR SYSTEMS INTO LARGER PLATFORMS.DRIVE THE DEFINITION OF PROTOCOLS, INTERFACES, AND STANDARDS FOR FABRIC AND SYSTEM COMMUNICATION.LEAD PERFORMANCE MODELING AND SIMULATION EFFORTS TO ENSURE EFFICIENT DATA FLOW AND MINIMIZE BOTTLENECKS.OVERSEE DESIGN VERIFICATION AND VALIDATION PROCESSES FOR FABRIC AND SYSTEM COMPONENTS.MENTOR JUNIOR TEAM MEMBERS AND CONTRIBUTE TO THE GROWTH OF THE ORGANIZATION¿S EXPERTISE IN FABRIC AND SYSTEM ARCHITECTURE.STAY ABREAST OF INDUSTRY TRENDS AND CONTRIBUTE TO OPENCHIP'S T...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11572 WE ARE ACTIVELY SEEKING A SENIOR DESIGN MANAGER TO JOIN OUR DYNAMIC AND GROWING DIGITAL DESIGN TEAM JOB RESPONSIBILITIES: RESPONSIBILITIES INCLUDE BUT NOT LIMITED TO:WORK ON DESIGN EXECUTION OF SILICON DESIGN.ORK ON SOC DFT ARCHITECTURE AND DFM CONCEPT.WORK ON IMPLEMENTATION AND VERIFICATION OF DFT MEASURES TO MEET PRODUCT SPECIFICATIONS AND PRODUCTION REQUIREMENTS.WORK CLOSELY WITH CROSS-FUNCTION TEAMS (DESIGN, PRODUCTION TEST AND QUALIFICATION) TO MEET TEST REQUIREMENTS WITH EFFECTIVE DFT SOLUTIONS.CONTRIBUTE TO TARGET COVERAGE REQUIREMENTS FOR LOGIC, MEMORIES, IO AND MIXED-SIGNAL IPS.GENERATE TEST PATTERNS AND SUPPORT POST-SILICON ATE AND QNR. REQUIRED SKILLS, QUALIFICATIONS AND EXPERIENCE: DEGREE/MASTE...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11567 DEVELOP AND MAINTAIN LOW-LEVEL SOFTWARE (BIOS AND FIRMWARE) FOR NOVEL HARDWARE ARCHITECTURES.DEVELOP AND MAINTAIN DEVICE DRIVERS FOR OPERATING SYSTEMS (MAINLY LINUX) TO EXPOSE NOVEL HARDWARE FEATURES (E.G., TELEMETRY) AND ACCELERATION, AS WELL AS TO SUPPORT THEIR EMULATION AND VIRTUALIZATION.PROVIDE MONITORING, INSTRUMENTATION, AND TELEMETRY TO EXPORT SYSTEM STATUS AND HEALTH METRICS.PROVIDE WORKLOAD CONTROL AND CONFIGURATION, AND API ENTRY POINTS TO ALLOW REMOTE OPERATION.CONFIGURE AND EXTEND EMULATION, SIMULATION, AND VIRTUALIZATION SOFTWARE.WORK WITH HARDWARE TEAMS, INFLUENCING HARDWARE/SOFTWARE CO-DESIGN.WORK WITH TEAMS DEVELOPING MIDDLEWARE, AND/OR CONTRIBUTE TO MIDDLEWARE.COLLABORATE WITH COLLEAGUES ...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11575 AS ANALOG ARCHITECTURE JUNIOR ENGINEER, YOU WILL WORK WITH A TEAM OF ENGINEERS TO DEVELOP AND VERIFY ANALOG AND POWER ARCHITECTURE FOR SYSTEM-ON-CHIP (SOC) DESIGNS, YOU WILL SUPPORT ANALOG IP INTEGRATION, POWER MANAGEMENT DEVELOPMENT AND VERIFICATION, VALIDATION OF POWER ESTIMATION MODEL AT CHIP AND SYSTEM LEVEL.IN THIS TEAM YOUR RESPONSIBILITY WILL INCLUDE, BUT NOT LIMITED, TO:DESIGN ANALOG IP TO IMPROVE PPA (PERFORMANCE-POWER-AREA).EVALUATE AND VERIFY ANALOG IP INTEGRATION.SUPPORT FULL-CHIP AMS VERIFICATION.SUPPORT MODELING AND ANALYSIS OF HIGH-SPEED INTERCONNECTS IN CHIPLETS,... REQUIRED SKILLS, QUALIFICATIONS AND EXPERIENCE: MASTER'S OR PHD IN COMPUTER ENGINEERING, ELECTRICAL ENGINEERING, OR RELATED FI...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11582 READING AND ANALYSING THE SYSTEM REQUIREMENTS AND ARCHITECTURE REQUIREMENT DOCUMENTS.DEVELOPING DETAILED TEST AND COVERAGE PLANS BASED ON THE ARCHITECTURE AND MICRO-ARCHITECTURE.DEVELOPING VERIFICATION METHODOLOGY.DEVELOPING VERIFICATION ENVIRONMENT DEVELOPMENT AND MAINTENANCE IN SYSTEMVERILOG/UVM/SYSTEMC/C++, INCLUDING ALL THE RESPECTIVE COMPONENTS.EXECUTING VERIFICATION PLANS, INCLUDING DESIGN BRING-UP, DV ENVIRONMENT BRING-UP, REGRESSIONS AND DEBUG OF THE TEST FAILURES.USING THE STANDARD TOOLS AND FLOWS OF THE VERIFICATION PROCESS CREATE AND EXECUTE TESTCASES TO VERIFY THE FUNCTIONALITY, PERFORMANCE, AND ROBUSTNESS IN EMBEDDED C AND SV.IDENTIFY, ISOLATE, AND DEBUG ISSUES FOUND DURING VERIFICATION, LEVER...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11622 THE MEMORY ARCHITECTURE TEAM CONSISTS OF A MULTI-DISCIPLINARY GROUP FOCUSED ON ARCHITECTURAL ASPECTS OF ALL MEMORIES IN THE SOC AND WORK ON POTENTIAL INNOVATIVE NON-VON-NEUMAN ARCHITECTURE. SPECIFICALLY, TEAM IDENTIFY THE OPTIMUM MEMORY MICRO-ARCHITECTURE CHOICES USING PERFORMANCE AND POWER ANALYSIS. THE TEAM WILL IDENTIFY THE ARCHITECTURE GUIDELINES FOR MEMORY SIZE, PARALLELISM AND PROTOCOL COMPLIANCE FOR THE SOC. JOB RESPONSIBILITIES: AS MEMORY ARCHITECTURE ENGINEER, YOU WILL WORK WITH A TEAM OF ENGINEERS TO DEFINE ARCHITECTURAL ASPECTS OF MEMORY INTEGRATION IN A SYSTEM-ON-CHIP (SOC) DESIGNS. THIS ENCOMPASSES CACHE MEMORIES, MAIN MEMORIES (DRAM, HBM), STORAGE (NVM) AND COMPUTE IN MEMORY (CIM) ARCHITECTUR...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11569 ARCHITECT AND DEFINE OVERALL SOC INCLUDING PROCESSING UNITS, HARDWARE ACCELERATORS, MEMORY, INTERCONNECT, INTERFACES AND ANALOG COMPONENTS.WORK HAND IN HAND WITH THE PRODUCT ARCHITECTS MAKING SURE HARDWARE ARCHITECTURE MEETS THE PRODUCT GOALS.CONDUCT SYSTEM-LEVEL MODELLING AND ANALYSIS TO OPTIMISE FOR POWER, PERFORMANCE, AREA AND COST.WORK WITH SOFTWARE AND FIRMWARE TEAMS FOR EFFICIENT AND OPTIMAL SYSTEM CO-DESIGN.EVALUATE NEW PROCESSES, TECHNOLOGIES, TRENDS, AND INDUSTRY STANDARDS.PERFORM HARD AND SOFT IP IDENTIFICATION, ANALYSIS AND SELECTION.LEAD ARCHITECTURE DEFINITION, REVIEWS AND PROVIDE TECHNICAL GUIDANCE.WORK WITH PEER MICRO ARCHITECT ACROSS THE ORGANIZATION ALIGNING PRODUCT AND ARCHITECTURE DEFINI...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11577 WE SEEK AN EXPERIENCED PLACE-AND-ROUTE ENGINEER TO MANAGE COMPLEX DIGITAL BACKEND FLOWS. THE ROLE REQUIRES INTERFACING DIGITAL FRONT-END DESIGNERS TO UNDERSTAND THE REQUIREMENTS THAT COME FROM RTL SYNTHESIS AND TO BE ABLE TO PARTITION ARCHITECTURES TO GIVE INPUTS AT THE GENERATION OF RATIONAL FLOORPLANNING AND TO DRIVE PHYSICAL ASPECTS EARLY IN THE DESIGN CYCLE. JOB RESPONSIBILITIES: ASSURE THE DELIVERABILITY OF THE MAIN PART OF THE CHIP,TAKING CARE OF P&R/STA FLOWS AND TOOLS AVAILABLE IN THE LATEST INDUSTRY,MEANING OF THE SYNTHESIS AND CAPABILITY TO DRIVE PLACE AND ROUTE OF COMPLEX BLOCKS THROUGH SIGNOFF FLOWS INCLUDING TIMING AND PHYSICAL VERIFICATION.DRIVE PLACE & ROUTE IN CHIP-LEVEL AND HIERARCHICAL PH...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11566 DEVELOP AND MAINTAIN LOW-LEVEL SOFTWARE (BIOS AND FIRMWARE) FOR NOVEL HARDWARE ARCHITECTURES.DEVELOP AND MAINTAIN DEVICE DRIVERS FOR OPERATING SYSTEMS (MAINLY LINUX) TO EXPOSE NOVEL HARDWARE FEATURES (E.G., TELEMETRY) AND ACCELERATION, AS WELL AS TO SUPPORT THEIR EMULATION AND VIRTUALIZATION.PROVIDE MONITORING, INSTRUMENTATION, AND TELEMETRY TO EXPORT SYSTEM STATUS AND HEALTH METRICS.PROVIDE WORKLOAD CONTROL AND CONFIGURATION, AND API ENTRY POINTS TO ALLOW REMOTE OPERATION.CONFIGURE AND EXTEND EMULATION, SIMULATION, AND VIRTUALIZATION SOFTWARE.WORK WITH HARDWARE TEAMS, INFLUENCING HARDWARE/SOFTWARE CO-DESIGN.WORK WITH TEAMS DEVELOPING MIDDLEWARE, AND/OR CONTRIBUTE TO MIDDLEWARE.COLLABORATE WITH COLLEAGUES ...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11568 AS SOC SENIOR ARCHITECTURE ENGINEER, YOU WILL WORK WITH A TEAM OF ENGINEERS TO DEVELOP AND VERIFY STATE-OF-THE-ART SYSTEM ON CHIP. YOU WILL BE WORKING ON ADVANCED DEVICE ARCHITECTURES, DESIGN DEFINITION, IMPLEMENTATION, AND VERIFICATION. YOU WILL ALSO BE DEVELOPING DESIGN EXAMPLES AND SIMULATION MODELS, ACCOMPANIED BY A RICH SET OF TECHNICAL DOCUMENTATION. IN THIS TEAM YOUR RESPONSIBILITY WILL INCLUDE, BUT NOT LIMITED, TO:DELIVER ARCHITECTURE SPECIFICATIONS AND REQUIREMENTS TO THE SOC TEAM, SUPPORT VERIFICATION AND SILICON VALIDATION TEAMS, AND WORK WITH SW TEAMS TO SUPPORT SUCCESSFUL DEPLOYMENTS OF THE SYSTEM.EVALUATE NEW IPS, DRIVING NEW IP DEPLOYMENTS AS WELL AS DEFINING SYSTEM WIDE GUIDELINES FOR IPS R...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11576 WORK ON DESIGN EXECUTION OF SILICON DESIGN.WORK ON SOC DFT ARCHITECTURE AND DFM CONCEPT.WORK ON IMPLEMENTATION AND VERIFICATION OF DFT MEASURES TO MEET PRODUCT SPECIFICATIONS AND PRODUCTION REQUIREMENTS.WORK CLOSELY WITH CROSS-FUNCTION TEAMS (DESIGN, PRODUCTION TEST AND QUALIFICATION) TO MEET TEST REQUIREMENTS WITH EFFECTIVE DFT SOLUTIONS.CONTRIBUTE TO TARGET COVERAGE REQUIREMENTS FOR LOGIC, MEMORIES, IO AND MIXED-SIGNAL IPS.GENERATE TEST PATTERNS AND SUPPORT POST-SILICON ATE AND QNR. REQUIRED SKILLS, QUALIFICATIONS AND EXPERIENCE: BACHELOR'S DEGREE IN ELECTRICAL OR ELECTRONIC ENGINEERING. BASIC UNDERSTANDING OF DIGITAL IC DESIGN PRINCIPLES.FAMILIARITY WITH RTL DESIGN CONCEPTS. EXPOSURE TO DFT CONCEPTS, IN...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11585 AS SOC INTERCONNECT SENIOR ARCHITECT, YOU WILL WORK WITH A TEAM OF ENGINEERS TO DEVELOP AND VERIFY STATE-OF-THE-ART MEMORY INTERFACE AND NETWORK-ON-CHIP IP CORES. YOU WILL BE WORKING ON ADVANCED DEVICE ARCHITECTURES, DESIGN DEFINITION, IMPLEMENTATION, AND VERIFICATION. YOU WILL ALSO BE DEVELOPING DESIGN EXAMPLES AND SIMULATION MODELS, ACCOMPANIED BY A RICH SET OF TECHNICAL DOCUMENTATION.IN THIS TEAM YOUR RESPONSIBILITY WILL INCLUDE, BUT NOT LIMITED, TO:ACTIVELY WORK WITH SOC ARCHITECTURE, VERIFICATION, PHYSICAL DESIGN TEAM, SOC FLOORPLAN, CORE TEAMS TO ACHIEVE SYSTEM TARGETS FOR PERFORMANCES, AREA AND POWER.COHERENT AND NON-COHERENT INTERCONNECTS WITHIN THE CHIP, COHERENCY PROTOCOL, DIRECTORY STRUCTURE, BA...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11557 DESIGN AND OPTIMIZE PRINTED CIRCUIT BOARDS (PCBS) FOR HIGH-PERFORMANCE ACCELERATOR SYSTEMS, INCLUDING HIGH-SPEED SIGNAL INTEGRITY AND POWER DELIVERY.ARCHITECT CHASSIS SOLUTIONS, FOCUSING ON STRUCTURAL INTEGRITY, THERMAL MANAGEMENT AND INTEGRATION WITH SYSTEM ENCLOSURES.DEVELOP AND IMPLEMENT ADVANCED COOLING STRATEGIES, INCLUDING AIR, LIQUID, AND HYBRID COOLING SYSTEMS, TAILORED TO HIGH-POWER ACCELERATOR PRODUCTS.COLLABORATE WITH SILICON, PACKAGING, AND SYSTEM TEAMS TO ENSURE SEAMLESS INTEGRATION OF HARDWARE AT THE BOARD AND CHASSIS LEVEL.CONDUCT THERMAL AND MECHANICAL SIMULATIONS TO VALIDATE DESIGNS AND ENSURE SYSTEM RELIABILITY UNDER VARIOUS OPERATING CONDITIONS. DEFINE AND ENFORCE DESIGN GUIDELINES, INCL...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11574 READING AND ANALYSING THE SYSTEM REQUIREMENTS AND ARCHITECTURE REQUIREMENT DOCUMENTS.DEVELOPING VERIFICATION ENVIRONMENT DEVELOPMENT AND MAINTENANCE IN SYSTEMVERILOG/UVM/SYSTEMC/C++, INCLUDING ALL THE RESPECTIVE COMPONENTS.EXECUTING VERIFICATION PLANS, INCLUDING DESIGN BRING-UP, DV ENVIRONMENT BRING-UP, REGRESSIONS AND DEBUG OF THE TEST FAILURES.USING THE STANDARD TOOLS AND FLOWS OF THE VERIFICATION PROCESS.CREATE AND EXECUTE TESTCASES TO VERIFY THE FUNCTIONALITY, PERFORMANCE, AND ROBUSTNESS IN EMBEDDED C AND SV.IDENTIFY, ISOLATE, AND DEBUG ISSUES FOUND DURING VERIFICATION.WORK CLOSELY WITH CROSS-FUNCTIONAL TEAMS TO ACHIEVE VERIFICATION CLOSURE, CONDUCTING COVERAGE ANALYSIS, BUG TRACKING, AND REGRESSION TE...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11581 WE SEEK AN EXPERIENCED PLACE-AND-ROUTE ENGINEER TO MANAGE DIGITAL BACKEND FLOWS. THE ROLE REQUIRES INTERFACING DIGITAL FRONT-END DESIGNERS TO UNDERSTAND THE REQUIREMENTS THAT COME FROM RTL SYNTHESIS AND TO BE ABLE TO PARTITION ARCHITECTURES TO GIVE INPUTS AT THE GENERATION OF RATIONAL FLOORPLANNING AND TO DRIVE PHYSICAL ASPECTS EARLY IN THE DESIGN CYCLE. JOB RESPONSIBILITIES: ASSURE THE DELIVERABILITY OF THE MAIN PART OF THE CHIP.TAKING CARE OF P&R/STA FLOWS AND TOOLS AVAILABLE IN THE LATEST INDUSTRY,MEANING OF THE SYNTHESIS AND CAPABILITY TO DRIVE PLACE AND ROUTE OF BLOCKS THROUGH SIGNOFF FLOWS INCLUDING TIMING AND PHYSICAL VERIFICATION. DRIVE PLACE & ROUTE IN CHIP-LEVEL AND HIERARCHICAL PHYSICAL IMPLEMEN...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11547 DELIVER TECHNICAL PRESENTATIONS TO ENGINEERING AND TECHNOLOGY LEADERS IN CUSTOMERS AND RESEARCH ORGANIZATIONS.DRIVE TECHNICAL DISCUSSIONS AND PREPARE THE TECHNICAL MATERIAL TO SUPPORT THEM.INFLUENCE IN TECHNOLOGY DECISIONS WITH ITS THOUGHT LEADERSHIP.WRITE CASE STUDIES / PAPERS IN COOPERATION WITH KEY CUSTOMERS AND PARTNERS.PLAN TECHNICAL TESTING AND PROOF OF CONCEPTS.ENGAGE WITH INTERNAL ENGINEERING AND ARCHITECTURE AREAS OF EXPERTISE. MANAGE TECHNOLOGY CLARIFICATIONS PROCESSES.PARTICIPATE IN CUSTOMERS BIDDING PROCESSES. REQUIREMENTS: THE CANDIDATE SHOULD BE EQUIPPED WITH A UNIQUE SKILLS-SET: SELF-STARTER, SELF-MOTIVATED, HUMILITY, EXCELLENT COMMUNICATIONS SKILLS, OUTSTANDING HUMAN QUALITIES AS HONESTY, I...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11560 DEFINE AND IMPLEMENT RAS STRATEGIES FOR ACCELERATOR PRODUCTS AT BOTH CHIP AND SYSTEM LEVELS, ENSURING HIGH RELIABILITY AND AVAILABILITY.DEVELOP FAULT-TOLERANT ARCHITECTURES, ERROR-DETECTION MECHANISMS AND RECOVERY PROTOCOLS.COLLABORATE WITH HARDWARE, FIRMWARE AND SOFTWARE TEAMS TO DESIGN RAS FEATURES SEAMLESSLY INTEGRATED ACROSS THE STACK.LEAD FAILURE ANALYSIS EFFORTS AND CONTRIBUTE TO CONTINUOUS IMPROVEMENT OF RAS METHODOLOGIES.DEFINE METRICS AND PERFORMANCE INDICATORS FOR RELIABILITY AND AVAILABILITY, DRIVING OPTIMIZATION THROUGH DESIGN AND TESTING PHASES.OVERSEE THE VALIDATION AND VERIFICATION OF RAS FEATURES, ENSURING COMPLIANCE WITH INDUSTRY STANDARDS.PROVIDE TECHNICAL GUIDANCE TO CROSS-FUNCTIONAL TEA...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11621 RESEARCH AND DEVELOP NOVEL MICRO-ARCHITECTURES AND DESIGNS FOR HIGH-PERFORMANCE MATRIX/TENSOR PROCESSING UNITS WITH A FOCUS ON ENABLING EFFICIENT SOFTWARE EXECUTION.INNOVATE AND ARCHITECT THE NEXT GENERATION OF HIGH-PERFORMANCE AI ACCELERATORS, CONSIDERING THE INTERPLAY BETWEEN HARDWARE CAPABILITIES AND SOFTWARE REQUIREMENTS.DRIVE SOFTWARE-HARDWARE CO-DESIGN EFFORTS TO OPTIMIZE OVERALL SYSTEM PERFORMANCE AND EFFICIENCY FOR AI WORKLOADS.SUPPORT THE DEVELOPMENT OF OPTIMIZED ARCHITECTURES CAPABLE OF SIGNIFICANTLY IMPROVING PPA (PERFORMANCE-POWER-AREA) WHILE EFFECTIVELY INTEGRATING CUSTOMER REQUIREMENTS AND CONSIDERING SOFTWARE IMPLICATIONS.EVALUATE THE ARCHITECTURAL IMPLEMENTATION OF VPU AND MPU DESIGNS, ENSU...

HOW TO APPLY? PLEASE SEND YOUR CV TO [email protected] - REFERENCE 11617 ABOUT THE FUNCTION:THE SOC ARCHITECTURE TEAM IS RESPONSIBLE TO DEFINE TOP LEVEL DELIVERABLES AND KEY FEATURES OF THE SOCS. SPECIFICALLY, TEAM WILL BE RESPONSIBLE TO RELEASE THE HAS, KPI, AND MAINTAIN CM PROCESS. TEAM WILL BE ALSO RESPONSIBLE FOR TOP LEVEL ASPECTS OF SECURITY AND PACKAGING. JOB RESPONSIBILITIES: AS SOC ARCHITECT ENGINEER, YOU WILL WORK WITH A TEAM OF ENGINEERS TO DEVELOP AND VERIFY STATE-OF-THE-ART SYSTEM ON CHIP. YOU WILL BE WORKING ON ADVANCED DEVICE ARCHITECTURES, DESIGN DEFINITION, IMPLEMENTATION, AND VERIFICATION. YOU WILL ALSO BE DEVELOPING DESIGN EXAMPLES AND SIMULATION MODELS, ACCOMPANIED BY A RICH SET OF TECHNICAL DOCUMENTATION.IN THIS TEAM YOUR RESPONSIBILITY WILL INCLUDE, BUT NOT...

KEY RESPONSIBILITIES:LEAD THE END-TO-END EXECUTION OF SYSTEM DEPLOYMENTS, INCLUDING HARDWARE-SOFTWARE INTEGRATION, TESTING, AND VALIDATION FOR SEMICONDUCTOR-BASED SYSTEMS.ENSURE ALL DEPLOYMENT ACTIVITIES ALIGN WITH COMPANY GOALS AND CUSTOMER REQUIREMENTS.:MANAGE SUBCONTRACTING EFFORTS FOR PCB DEVELOPMENT, COMPONENT SOURCING, AND MANUFACTURING PARTNERS.NEGOTIATE CONTRACTS, MONITOR VENDOR PERFORMANCE, AND ENSURE COMPLIANCE WITH QUALITY STANDARDS. DEVELOP PROJECT PLANS, TIMELINES, AND RESOURCE ALLOCATION STRATEGIES TO DELIVER PROJECTS EFFICIENTLY.-MONITOR PROGRESS, IDENTIFY RISKS, AND IMPLEMENT MITIGATION STRATEGIES TO KEEP PROJECTS ON TRACK. PROVIDE TECHNICAL GUIDANCE ON COMPLEX DEPLOYMENT CHALLENGE.COLLABORATE WITH ENGINEERING TEAMS TO RESOLVE ISSUES RELATED TO SYSTEM INTEGRATION, TESTING, ...

THE ROLE: THE DIRECTOR OF AI SAFETY WILL BE RESPONSIBLE FOR ENSURING THAT OUR AI SYSTEMS ARE SECURE, ETHICAL, AND ALIGNED WITH INDUSTRY SAFETY STANDARDS. THIS ROLE DEMANDS A VERTICALLY INTEGRATED APPROACH, ADDRESSING AI SECURITY FROM HIGH-LEVEL APPLICATIONS DOWN TO LOW-LEVEL IMPLEMENTATION. THE IDEAL CANDIDATE WILL LEAD THE DEVELOPMENT OF SAFETY MECHANISMS, GUARDRAILS, AND VALIDATION FRAMEWORKS TO BUILD TRUSTED AI SYSTEMS. KEY RESPONSIBILITIES:DEFINE AND IMPLEMENT AI SAFETY AND SECURITY STRATEGIES ACROSS THE SOFTWARE STACK, ENSURING COMPLIANCE WITH ETHICAL AI PRINCIPLES, SECURITY BEST PRACTICES, AND REGULATORY REQUIREMENTS.DEVELOP AND OVERSEE THE IMPLEMENTATION OF AI GUARDRAILS, MODEL VALIDATION FRAMEWORKS, AND TRUSTWORTHINESS ASSESSMENTS FOR AI APPLICATIONS.CONDUCT END-TO-END VALIDATION A...

THE ROLE: THE DIRECTOR OF AI APPLICATIONS  WILL DRIVE THE ADOPTION OF OUR AI TECHNOLOGIES IN REAL-WORLD INDUSTRIES SUCH AS HEALTHCARE, CYBERSECURITY, AND ROBOTICS. THIS ROLE INVOLVES COLLABORATING WITH PARTNERS AND CUSTOMERS TO DEVELOP TAILORED AI APPLICATIONS WHILE LEVERAGING STATE-OF-THE-ART AI FRAMEWORKS. THE IDEAL CANDIDATE WILL HAVE DEEP EXPERTISE IN LLM FINE-TUNING, AI WORKFLOW AUTOMATION, AND HIGH-PERFORMANCE COMPUTING APPLICATIONS. KEY RESPONSIBILITIES: ¿LEAD THE DEVELOPMENT OF AI-POWERED APPLICATIONS ACROSS INDUSTRIES SUCH AS HEALTHCARE, CYBERSECURITY, ROBOTICS, AND HPC.¿COLLABORATE WITH CUSTOMERS AND PARTNERS TO DESIGN AND IMPLEMENT DOMAIN-SPECIFIC AI SOLUTIONS LEVERAGING TECHNOLOGY.¿SPEARHEAD AI FINE-TUNING INITIATIVES, WORKING WITH LARGE LANGUAGE MODELS (LLMS) AND MULTIMODAL AI...

AS A FUNCTIONAL VERIFICATION ENGINEER, YOU WILL BE INTERFACING WITH ARCHITECTURE, DESIGN, PHYSICAL IMPLEMENTATION AND SOFTWARE TEAMS IN ORDER TO MAKE SURE THAT THE SYSTEMS ARE PERFORMING TO THE HIGHEST LEVEL. YOUR WORK MAY INVOLVE HIGH-LEVEL MODELLING, UVM, HW/SW CO-DEBUG, SIMULATION ACCELERATION SUPPORT. THE ROLE:READING AND ANALYSING THE SYSTEM REQUIREMENTS AND ARCHITECTURE REQUIREMENT DOCUMENTS. DEVELOPING VERIFICATION ENVIRONMENT DEVELOPMENT AND MAINTENANCE IN SYSTEMVERILOG/UVM/SYSTEMC/C++, INCLUDING ALL THE RESPECTIVE COMPONENTS SUCH AS STIMULUS, CHECKERS, ASSERTIONS, TRACKERS, AND COVERAGE.EXECUTING VERIFICATION PLANS, INCLUDING DESIGN BRING-UP, DV ENVIRONMENT BRING-UP, REGRESSIONS AND DEBUG OF THE TEST FAILURES. USING THE STANDARD TOOLS AND FLOWS OF THE VERIFICATION PROCESS (SIMULAT...

SENIOR FUNCTIONAL VERIFICATION ENGINEE  KEY RESPONSIBILITIES:READING AND ANALYSING THE SYSTEM REQUIREMENTS AND ARCHITECTURE REQUIREMENT DOCUMENTS.DEVELOPING VERIFICATION ENVIRONMENT DEVELOPMENT AND MAINTENANCE IN SYSTEMVERILOG/UVM/SYSTEMC/C++. INCLUDING ALL THE RESPECTIVE COMPONENTS.EXECUTING VERIFICATION PLANS, INCLUDING DESIGN BRING-UP, DV ENVIRONMENT BRING-UP, REGRESSIONS AND DEBUG OF THE TEST FAILURES.-USING THE STANDARD TOOLS AND FLOWS OF THE VERIFICATION PROCESS.CREATE AND EXECUTE TESTCASES TO VERIFY THE FUNCTIONALITY, PERFORMANCE, AND ROBUSTNESS IN EMBEDDED C AND SV. IDENTIFY, ISOLATE, AND DEBUG ISSUES FOUND DURING VERIFICATION.WORK CLOSELY WITH CROSS-FUNCTIONAL TEAMS TO ACHIEVE VERIFICATION CLOSURE, CONDUCTING COVERAGE ANALYSIS, BUG TRACKING, AND REGRESSION TESTING.PARTICIPATION TO...

DIGITAL SENIOR ENGINEER. THE ROLE: RESPONSIBILITIES INCLUDE BUT NOT LIMITED TO: - TO DRIVE DESIGN EXECUTION OF SILICON DESIGN FROM DEFINITION THROUGH PRODUCT LAUNCH AND ACTS AS PRIMARY POINT OF CONTACT FOR A IP DEVELOPMENT AND IP INTEGRATION IN SOC.- TO COLLABORATE WITH A MULTIDISCIPLINARY PROJECT TEAM DESIGN FOR SILICON PRODUCTS.- TO WORK IN TIGHT COLLABORATION WITH EMULATION, VERIFICATION, AND VALIDATION DEVELOPMENT TEAMS TO ENSURE BUG FREE DESIGN.- TO WORK ACROSS IP AND SOC DEVELOPMENT TEAMS TO ENSURE DELIVERY OF COMPLEX SILICON DESIGN PROJECTS.-TO ENSURE THAT THE FINAL DESIGN MEETS THE KEY FACTORS- TO WORK CONTINUOUSLY TO IMPROVE SILICON DEVELOPMENT PROCESSES AND ARCHITECTURE DEFINITION- TO WORK WITH POST-SILICON VALIDATION, MANUFACTURING, PLATFORM, AND SOFTWARE STAKEHOLDERS THROUGHOUT...

THE ROLE:RESPONSIBILITIES INCLUDE BUT NOT LIMITED TO:  TO DRIVE DESIGN EXECUTION OF SILICON DESIGN FROM DEFINITION THROUGH PRODUCT LAUNCH AND ACTS AS PRIMARY POINT OF CONTACT FOR A IP/PRODUCT DEVELOPMENT-- TO COLLABORATE WITH A MULTIDISCIPLINARY PROJECT TEAM DESIGN FOR SILICON PRODUCTS WITH FOCUS ON PRODUCT EXECUTION.TO WORK IN TIGHT COLLABORATION WITH FIRMWARE/SOFTWARE, EMULATION, VERIFICATION, AND VALIDATION DEVELOPMENT TEAMS TO ENSURE BUG FREE DESIGN-TO WORK ACROSS IP AND SOC DEVELOPMENT TEAMS TO ENSURE DELIVERY OF COMPLEX SILICON DESIGN PROJECTS, ENSURING QUALITY AND PERFORMANCE-TO ENSURE THAT THE FINAL DESIGN MEET THE KEY FACTORS SUCH- TO WORK CONTINUOUSLY TO IMPROVE SILICON DEVELOPMENT PROCESSES AND ARCHITECTURE DEFINITION- TO WORK WITH POST-SILICON VALIDATION, MANUFACTURING, PLATFOR...

COMPILER ENGINEER JOB RESPONSIBILITIES: MAKE INDEPENDENT TECHNICAL CONTRIBUTIONS TO HELP THEIR TEAM DELIVER ITS COMMITMENTS. IN PARTICULAR: ¿WRITE CODE TO EXTEND COMPILER FRAMEWORKS (E.G., GCC, LLVM), ENABLING USAGE OF NOVEL HARDWARE FEATURES AND ACCELERATION, AND IMPROVING THE QUALITY OF CODE GENERATED FOR THESE TARGETS.¿THIS INCLUDES BOTH ¿TRADITIONAL(HIGH-LEVEL LANGUAGE TO BINARY) COMPILERS AS WELL AS THOSE MANIPULATING ML INTERMEDIATE REPRESENTATIONS (E.G., MODEL GRAPHS) INTERACT WITH ICS FROM THEIR AND OTHER PROJECTS TO UNBLOCK THEMSELF, OR TO REACH CONSENSUS ON SMALL TECHNICAL TOPICS. IN PARTICULAR: ¿WORK WITH ML/AI AND HARDWARE TEAMS, CONNECTING THEIR RESPECTIVE REQUIREMENTS AND OFFERINGS, INFLUENCING HARDWARE/SOFTWARE CO-DESIGN. ¿IN OTHER CASES, UNDERSTAND ML/AI WORKLOADS, BOTH IND...

KEY RESPONSABILITIES:MANAGE A TEAM OF ENGINEERS WORKING IN THE RELEVANT TECHNICAL SPACE. IN PARTICULAR:CREATE A WELCOMING WORK ENVIRONMENT IN THEIR ORG AND STRIVE FOR REPORTSMOTIVATION, WELL-BEING, AND PROFESSIONAL GROWTH OPPORTUNITIES.PROVIDE TECHNICAL AND PROFESSIONAL GUIDANCE TO THEIR REPORTS. GIVE FEEDBACK, PRIORITIES, AND HIGHER- LEVEL CONTEXT.TAKE PART IN TASK TRACKING AND ASSIGNMENT, MONITORING THEIR REPORTSWORKLOADS AS WELL AS HOW TASKS ARE CONTRIBUTING TO DEVELOPMENT AND BUSINESS GOALS.HOST REGULAR 1:1 AND TEAM-WIDE MEETINGS FOR FREQUENT COMMUNICATION AND OVERALL TEAM AWARENESS.HOST REGULAR PERFORMANCE CONVERSATIONS WITH REPORTS AND COMPLETE THE PERIODICAL PERFORMANCE APPRAISAL PROCESS FOR THEIR TEAM. DETERMINE CLEAR PERFORMANCE GOALS, KEEP TRACK OF THEIR PROGRESS, AND TAKE PART I...

KEY RESPONSIBILITIES:· RESEARCH, DESIGN, AND IMPLEMENT MULTI-AGENT LLM-BASED ARCHITECTURES TO SOLVE REAL-WORLD AI CHALLENGES.· DEVELOP AND OPTIMIZE ALGORITHMS FOR AGENT COORDINATION, COMMUNICATION, AND COLLABORATION IN COMPLEX ENVIRONMENTS.· WORK WITH CUTTING-EDGE AI TECHNIQUES SUCH AS REINFORCEMENT LEARNING, SELF-SUPERVISED LEARNING, AND META-LEARNING TO ENHANCE MULTI-AGENT PERFORMANCE.· COLLABORATE WITH HARDWARE AND SOFTWARE ENGINEERS TO CO-DESIGN AI MODELS OPTIMIZED FOR OPENCHIP¿S CUSTOM SILICON SOLUTIONS.· EXPERIMENT WITH DECENTRALIZED AI MODELS AND FEDERATED LEARNING APPROACHES FOR MULTI-AGENT SYSTEMS.· IMPLEMENT LARGE-SCALE DISTRIBUTED TRAINING PIPELINES FOR MULTI-AGENT REINFORCEMENT LEARNING.· CONDUCT PERFORMANCE ANALYSIS AND BENCHMARKING OF AI WORKLOADS ON CUSTOM ACCELERATORS.· STA...

THE ROLE: LEAD BY EXAMPLE THE CORPORATE IT INFRASTRUCTURE TEAM (4 ENGINEERS AND GROWING) FOR THE ORGANIZATION.BE THE TECHNICAL SENIOR ENGINEER IN MICROSOFT, LINUX AND NETWORKING, AND BECOME SUBJECT MATTER EXPERT (SME) IN IT INFRAESTRUCTURE FOR THE WHOLE COMPANY.DRIVE THE IMPLEMENTATION OF IT PROCESSES DESIGNED BY THE IT MANAGER AND THE CYBERSECURITY LEAD.RADICAL HANDS-ON APPROACH COMBINED WITH STRATEGIC THINKING.TAKE OWNERSHIP OF RELATIONSHIPS WITH THE INTERNAL SYSTEM ADMINISTRATORS OF OUR DIFFERENT ENGINEERING TEAMS ACROSS THE GLOBE (10 AND GROWING).WORK CLOSELY WITH THE CYBERSECURITY LEAD AND IT MANAGER TO ENSURE ALIGNMENT WITH SECURITY AND CORPORATE STRATEGY. QUALIFICATIONS: DEGREE IN COMPUTER SCIENCE, INFORMATION TECHNOLOGY, OR RELATED FIELD.7+ YEARS OF EXPERIENCE IN IT INFRASTRUCTURE,...

KEY RESPONSIBILITIES: ACT AS A TRUSTED ADVISOR AND PARTNER TO STAKEHOLDERS ACROSS THE ORGANIZATION TO IDENTIFY AND ADDRESS PROCESS IMPROVEMENT OPPORTUNITIES.LEAD AND MANAGE END-TO-END DIGITALIZATION PROJECTS, ENSURING ALIGNMENT WITH COMPANY STRATEGY, USING TOOLS SUCH AS DOCUWARE, CRM, ERP, MICROSOFT, ETC.COORDINATE EXTERNAL PROVIDERS AND INTERNAL TEAMS, PARTICULARLY COLLABORATING WITH THE IT DEPARTMENT TO IMPLEMENT SOLUTIONS EFFECTIVELY.ANALYZE AND MAP CURRENT PROCESSES (AS-IS) AND DESIGN OPTIMIZED FUTURE PROCESSES (TO-BE).PROPOSE, DEFINE, AND IMPLEMENT NEW PROCESSES TO IMPROVE OPERATIONAL EFFICIENCY.PERFORM BASIC TECHNICAL CONFIGURATIONS OF IMPLEMENTED DIGITAL TOOLS WHEN NEEDED.DRIVE CHANGE MANAGEMENT INITIATIVES TO ENSURE THE SUCCESSFUL ADOPTION OF NEW PROCESSES AND TOOLS.EXCELLENT COMMU...

KEY RESPONSIBILITIES: READING AND ANALYSING THE SYSTEM REQUIREMENTS AND ARCHITECTURE REQUIREMENT DOCUMENTS.DEVELOPING DETAILED TEST AND COVERAGE PLANS BASED ON THE ARCHITECTURE AND MICRO-ARCHITEC-TURE.DEVELOPING VERIFICATION METHODOLOGY, ENSURING SCALABILITY AND PORTABILITY ACROSS ENVIRON-MENTS.DEVELOPING VERIFICATION ENVIRONMENT DEVELOPMENT AND MAINTENANCE IN SYSTEMVERI-LOG/UVM/SYSTEMC/C++, INCLUDING ALL THE RESPECTIVE COMPONENTS SUCH AS STIMULUS, CHECKERS, ASSERTIONS, TRACKERS, AND COVERAGE.EXECUTING VERIFICATION PLANS, INCLUDING DESIGN BRING-UP, DV ENVIRONMENT BRING-UP, REGRES-SIONS AND DEBUG OF THE TEST FAILURES.USING THE STANDARD TOOLS AND FLOWS OF THE VERIFICATION PROCESS.CREATE AND EXECUTE TESTCASES TO VERIFY THE FUNCTIONALITY, PERFORMANCE, AND ROBUSTNESS IN EM-BEDDED C AND SV.IDENT...

KEY RESPONSIBILITIES:MAKE INDEPENDENT TECHNICAL CONTRIBUTIONS TO HELP THEIR TEAM DELIVER ITS COMMITMENTS. IN PARTICULAR: COLLECT, CLEAN, AND MAINTAIN DATA FOR ML MODEL TRAINING AND EVALUATION, INCORPORATING DATA GOVERNANCE TO COMPLY WITH PRIVACY REQUIREMENTS.  IMPLEMENT PUBLISHED ML MODELS AND REPLICATE EXPERIMENTAL RESULTS. DEVELOP NEW ML MODELS, IDENTIFY TRAINING REGIMES, AND PROVIDE QUALITY EVALUATIONS. DOCUMENT THE FOLLOWED METHODOLOGIES AND MAIN FINDINGS.ASSESS AND OPTIMIZE MODEL PERFORMANCE AND RESOURCE CONSUMPTION (POWER, MEMORY, CPU/GPU/NNU...), CONSIDERING FUNCTIONAL AND NON-FUNCTIONAL REQUIREMENTS (QPS, PRIVACY CONSTRAINTS...). DEPLOY ML MODELS IN PRODUCTION, INTERACTING WITH INFRASTRUCTURE TEAMS. CONTRIBUTE TO MODEL RELEASE, QUALITY ASSESSMENT, AND DEBUGGING. DEVELOP AND MAINTAI...

KEY RESPONSIBILITIES:WORK ON DESIGN EXECUTION OF SILICON DESIGN.WORK ON SOC DFT ARCHITECTURE AND DFM CONCEPT.WORK ON THE IMPLEMENTATION AND VERIFICATION OF DFT MEASURES TO MEET PRODUCT SPECIFICATIONS AND PRODUCTION REQUIREMENTS.WORK CLOSELY WITH CROSS-FUNCTION TEAMS (DESIGN, PRODUCTION TEST AND QUALIFICATION) TO MEET TEST REQUIREMENTS WITH EFFECTIVE DFT SOLUTIONS.CONTRIBUTE TO TARGET COVERAGE REQUIREMENTS FOR LOGIC, MEMORIES, IO AND MIXED-SIGNAL IPS.GENERATE TEST PATTERNS AND SUPPORT POST-SILICON ATE AND QNR. REQUIRED SKILLS AND EXPERIENCE:BSC/MSC IN ELECTRICAL/ELECTRONIC ENGINEERING (OR IN A RELATED FIELD) WITH 10+ YEARS OF EXPERIENCE GAINED IN IC DIGITAL DESIGN WITH MULTIPLE CYCLES OF DFT AND RTL DESIGN.GOOD KNOWLEDGE OF MBIST INSERTION, COMPRESSION INSERTION, SCAN STITCHING, OCC INSERTI...

KEY RESPONSIBILITIES:LEAD THE DEVELOPMENT AND OPTIMIZATION OF AI MODELS TO RUN EFFICIENTLY ON OUR¿S CUSTOM HARDWARE PLATFORMS. DRIVE RESEARCH AND IMPLEMENTATION OF MODEL OPTIMIZATION TECHNIQUES SUCH AS QUANTIZATION, MIXED-PRECISION TRAINING, PRUNING, AND MODEL DISTILLATION.WORK CLOSELY WITH THE HARDWARE AND AI SOFTWARE TEAMS TO ALIGN AI MODEL EFFICIENCY WITH OUR¿S COMPUTE ARCHITECTURE.DESIGN AND OPTIMIZE AI MODEL TRAINING AND INFERENCE WORKFLOWS FOR LARGE-SCALE DEPLOYMENTS.OVERSEE BENCHMARKING AND PERFORMANCE EVALUATION OF AI MODELS ACROSS DIFFERENT HARDWARE CONFIGURATIONS.ENSURE OUR¿S AI STACK COMPETES AT THE HIGHEST LEVEL AGAINST INDUSTRY-LEADING AI ACCELERATORS. REPRESENT OUR ORGANIZATION IN AI MODEL OPTIMIZATION RESEARCH COMMUNITIES AND TECHNICAL WORKING GROUPS.YOU WILL BE REPORTING TO...

KEY RESPONSIBILITIES:LEAD AND MENTOR A TEAM OF AI ENGINEERS, FOSTERING INNOVATION AND TECHNICAL EXCELLENCE.DEFINE AND OVERSEE THE ROADMAP FOR AI DEVELOPMENT, ENSURING ALIGNMENT WITH OPENCHIP¿S LONG-TERM VISION.ARCHITECT AND IMPLEMENT SCALABLE BACKEND SYSTEMS THAT SUPPORT AI-DRIVEN FUNCTIONALITIES, LEVERAGING MODERN FRAMEWORKS AND METHODOLOGIES.OPTIMIZE AI WORKLOADS FOR CUSTOM SILICON, WORKING CLOSELY WITH HARDWARE AND SOFTWARE TEAMS.RESEARCH AND INTEGRATE ADVANCED AI TECHNIQUES SUCH AS REINFORCEMENT LEARNING, SELF-SUPERVISED LEARNING, AND FEDERATED LEARNING.DESIGN AND MANAGE DISTRIBUTED AI SYSTEMS, ENSURING EFFICIENT TRAINING AND INFERENCE FOR LARGE-SCALE MODELS.COLLABORATE WITH CROSS-FUNCTIONAL TEAMS TO CO-DEVELOP AI SOLUTIONS THAT ENHANCE CHIP PERFORMANCE AND EFFICIENCY.STAY AHEAD OF AI ...

KEY RESPONSIBILITIES: BECOME THE INTERNAL LEVEL 2 SPECIALIST FOR ALL MICROSOFT TECHNOLOGIES.ASSIST THE LEAD INFRASTRUCTURE ENGINEER IN THE ARCHITECTURAL DESIGN OF NEW MICROSOFT SERVICES.ADMINISTRATION OF MICROSOFT 365 SUITE, WITH EXPERIENCE ADMINISTRATING SHAREPOINT AND TEAMS, IN A HYBRID AD SCENARIO WITH ENTRA AND INTUNE.ADMINISTRATION OF EXCHANGE ONLINE.SUPPORT L1 SERVICE DESK AS A MICROSOFT SPECIALIST.IMPLEMENT IT CHANGES AND SOLVE IT PROBLEMS, WITH HELP FROM L3 WHEN NEEDED.POSSIBILITY OF GROWING INTERNALLY TO DEVELOP AND MANAGE A LARGER INTERNAL IT INFRASTRUCTURE TEAM, FOSTERING SMOOTH COLLABORATION AND ALIGNMENT WITH COMPANY GOALS.ENSURE ADHERENCE TO SERVICE LEVEL AGREEMENTS (SLAS) BETWEEN IT AND OTHER COMPANY DEPARTMENTS.SUPPORT STRATEGIC IT INITIATIVES AND DRIVE CONTINUOUS IMPROVEME...

KEY RESPONSIBILITIES:· DESIGN, TRAIN, AND OPTIMIZE LARGE-SCALE AI MODELS, INCLUDING LLMS AND SIMILAR ARCHITECTURES.· COLLABORATE WITH HARDWARE AND SOFTWARE ENGINEERS TO ENSURE EFFICIENT MODEL DEPLOYMENT ON CUSTOM SILICON SOLUTIONS.· DEVELOP NEW TECHNIQUES FOR IMPROVING TRAINING EFFICIENCY, MODEL ACCURACY, AND HARDWARE UTILIZATION.· IMPLEMENT DISTRIBUTED TRAINING STRATEGIES FOR LARGE-SCALE MODELS ACROSS HIGH-PERFORMANCE COMPUTING INFRASTRUCTURES.· STRONG PROGRAMMING SKILLS IN PYTHON, (GO, C++,¿IS CONSIDERED A PLUS).· EXPLORE AND IMPLEMENT ADVANCED AI/ML TECHNIQUES, SUCH AS SPARSITY, QUANTIZATION, AND KNOWLEDGE DISTILLATION.· WORK WITH STATE-OF-THE-ART FRAMEWORKS SUCH AS TENSORFLOW, PYTORCH, JAX, AND HUGGING FACE TRANSFORMERS.· CONDUCT PERFORMANCE BENCHMARKING AND PROFILING OF ML WORKLOADS O...

KEY RESPONSIBILITIES:DEVELOP, OPTIMIZE, AND MAINTAIN SCALABLE BACKEND SERVICES SUPPORTING AI-DRIVEN APPLICATIONS AND PIPELINES.DESIGN AND IMPLEMENT APIS FOR AI MODEL INFERENCE, TRAINING, AND DATA PROCESSING.COLLABORATE WITH AI AND HARDWARE ENGINEERS TO INTEGRATE AI FUNCTIONALITIES INTO CUSTOM SILICON SOLUTIONS.WORK WITH DATABASES AND STORAGE SOLUTIONS TO MANAGE AND PROCESS LARGE-SCALE AI DATASETS EFFICIENTLY.ENSURE SECURITY, PERFORMANCE, AND RELIABILITY IN AI-BASED BACKEND ARCHITECTURES.DEPLOY AND MANAGE AI MODELS IN CLOUD AND ON-PREMISE ENVIRONMENTS, OPTIMIZING FOR PERFORMANCE AND COST.STAY UP TO DATE WITH ADVANCEMENTS IN AI SOFTWARE ENGINEERING AND BACKEND TECHNOLOGIES TO BRING INNOVATIVE SOLUTIONS INTO OPENCHIP¿S AI STRATEGY. QUALIFICATIONS:BSC OR MSC IN COMPUTER SCIENCE, SOFTWARE ENGIN...

KEY RESPONSIBILITIES:· RESEARCH, DEVELOP, AND IMPLEMENT MODEL OPTIMIZATION TECHNIQUES SUCH AS QUANTIZATION, PRUNING, AND DISTILLATION TO IMPROVE AI MODEL EFFICIENCY.· DESIGN AND OPTIMIZE AI MODELS FOR DEPLOYMENT ON (CUSTOM) AI ACCELERATORS.· WORK CLOSELY WITH HARDWARE AND SOFTWARE TEAMS TO CO-DESIGN AI MODELS THAT LEVERAGE  UNIQUE SILICON CAPABILITIES.· DEVELOP STRATEGIES FOR REDUCING MEMORY FOOTPRINT, ENERGY CONSUMPTION, AND LATENCY IN AI INFERENCE.· BENCHMARK AND ANALYZE AI WORKLOADS ON VARIOUS ARCHITECTURES TO DRIVE OPTIMIZATION STRATEGIES.· STAY UP TO DATE WITH THE LATEST ADVANCEMENTS IN AI MODEL OPTIMIZATION, EDGE AI DEPLOYMENT, AND HARDWARE-AWARE NEURAL NETWORK DESIGN.· PARTICIPATE IN TECHNICAL DISCUSSIONS AND CONTRIBUTE TO OUR¿S AI RESEARCH AND DEVELOPMENT ROADMAP. QUALIFICATIONS:BS...

WE ARE SEEKING A VISIONARY AND RESULTS-DRIVEN CHIEF ARCHITECT TO LEAD OUR EFFORTS IN DESIGNING AND DEPLOYING CUTTING-EDGE DATA CENTER SYSTEMS, FULL-STACK COMPUTING SOLUTIONS, AND ADVANCED FABRICS. AS THE CHIEF ARCHITECT, YOU WILL PLAY A PIVOTAL ROLE IN SHAPING THE FUTURE OF HIGH-PERFORMANCE COMPUTING (HPC), ARTIFICIAL INTELLIGENCE (AI), AND CLOUD INFRASTRUCTURE BY DRIVING INNOVATION IN SYSTEM ARCHITECTURE, INTERCONNECTS, AND RAS TECHNOLOGIES.IN THIS STRATEGIC LEADERSHIP ROLE, YOU WILL OVERSEE THE DESIGN AND IMPLEMENTATION OF END-TO-END COMPUTING SYSTEMS THAT POWER OUR NEXT-GENERATION DATACENTERS. YOU WILL COLLABORATE WITH CROSS-FUNCTIONAL TEAMS TO ENSURE SEAMLESS INTEGRATION OF HARDWARE, SOFTWARE, NETWORKING, AND ADVANCED COOLING SOLUTIONS, WHILE MAINTAINING A RELENTLESS FOCUS ON PERFORMAN...